1. Field of the Invention
The present invention relates to a technology for manufacturing a filed effect transistor.
2. Description of the Related Art
A wide band-gap semiconductor such as III-V nitride compound is preferably used as a material for high-power, high-frequency, and high-temperature semiconductor devices, because the wide band-gap semiconductor has high breakdown voltage and good thermal conductivity. For example, a field effect transistor (FET) having an AlGaN/GaN heterostructure induces two-dimensional electron gas at an interface by piezoelectric effect. The two-dimensional electron gas has high electron mobility and high career density so that it is widely tested for a practical use. In addition, an AlGaN/GaN heterostructure field effect transistor (HFET) has a low ON-resistance and a fast switching speed, which realizes a high temperature operation. The above characteristics are preferable for power switching application.
Generally, the AlGaN/GaN HFET is configured as a normally-on type device, in which current flows when bias is not applied to a gate and the current is blocked when negative voltage is applied to the gate. However, for the power switching application, it is more preferable to use a normally-off type device, in which the current is blocked when bias is not applied to the gate and the current flows when positive voltage is applied to the gate, so that a security is assured even when a failure occurs in the device.
To realize the normally-off type device, it is necessary to employ a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. FIG. 5 is a schematic side view of a conventional MOSFET 500 as disclosed in a document by Matocha K., Chow T. P., and Gutmann R. J., “High-voltage normally off GaN MOSFETs on sapphire substrates”, IEEE Transactions on Electron Devices. vol. 52, No. 1, pp. 6-10 (2005). A buffer layer 502 and a p-type gallium nitride (p-GaN) layer 504 are formed in that order on a substrate 501 in the MOSFET 500. Two n+GaN regions 505a and 505b, as contact layers to realize an ohmic contact between source and drain regions, are formed on a portion of the p-GaN layer 504 by an ion implantation method. An n−-GaN region 503 called a reduced surface field (RESURF) layer is formed between a gate region and a drain region by the ion implantation method, so that a local electric field concentration between the gate and the drain regions is reduced and the breakdown voltage of the device is enhanced. An oxide film 506 made of SiO2 or the like is deposited as a gate insulating film and a gate electrode 507 is formed on the oxide film 506. The gate electrode 507 can be made of metal such as poly-Si, Ni/Au, and WSi. A source electrode 508 and a drain electrode 509 are formed on the n+GaN regions 505a and 505b, respectively. The source electrode 508 and the drain electrode 509 are made of metal that realizes the ohmic contact to the n+GaN region, such as Ti/Al or Ti/AlSi/Mo.
For realizing preferable channel mobility, the MOSFET needs to be configured in such a manner that a low interface state is maintained between the oxide film and the semiconductor. With a normal Si-based MOSFET, an SiO2 thermally-oxidized film made of thermally-oxidized Si is used as the oxide film, so that preferably low interface state is realized. On the other hand, with a nitride-compound-based MOSFET, a preferable thermally-oxidized film cannot be obtained, so that the oxide film is generally formed from SiO2 by a plasma enhanced chemical vapor deposition (p-CVD) method.
For forming the n+GaN region and the n−-GaN region, the ion implantation method is conventionally used as described above. In the ion implantation method, an annealing process for restoring crystal defect and activating implanted impurity ions is performed after implanting predetermined impurity ions. If the semiconductor is made of GaN, because crystal binding is strong, the annealing process needs to be performed at a high temperature such as more than 1200° C.
However, if the impurity ions are not sufficiently activated by the annealing process, a leakage current increases, the electron mobility in the RESURF layer is degraded, and breakdown voltage characteristic of the RESURF layer is enhanced, due to inactive impurity ions.
On the other hand, if the annealing process is performed at a high temperature for fully activating the impurity ions, pits occur on the surface of a GaN layer of the oxide film, resulting in degrading quality of GaN/oxide film interface and channel mobility.